Wednesday, 13 July 2011

July News: Design Checklist: Is Your FPGA Design Reusable?

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Inside Edge Monthly Enewsletter
   July 2011   www.altera.com  

Monthly Spotlight

Design Checklist: Is Your FPGA Design Reusable?
Read this article to learn how design reuse improves the quality of your FPGA design, shortens your design and verification cycle, and allows faster time to market. The design checklist helps you create a reusable FPGA design for your next project. Read more and get on the right track.
  Design Checklist: Is Your FPGA Design Reusable?


Software, Intellectual Property, and Development Kits

Buy Quartus II Software and Get a Free Nios II Processor
Get a free Nios® II processor license when you purchase Quartus® II Subscription Edition software. Offer good through September 30, 2011.


Download Now! Quartus II Software v11.0 Service Pack 1
This service pack includes initial support for Stratix® V GX and GT devices and final power models for Cyclone® IV GX devices.

Technology and End Markets

Webcast: Accelerate Video Design with FPGAs and IP Cores
Find out how FPGAs provide a customizable solution and quick intellectual property (IP) integration to build your video design faster.

Video: Watch a 5-Minute Online Demo on VEEK with VIP Suite
See the CycloneIV E FPGA-based Video and Embedded Evaluation Kit (VEEK) running video format conversion using Altera's Video and Image Processing (VIP) Suite.)

Webcast: Accelerate Your FPGA-Based DSP Designs
See how a design framework with IP cores and a variable-precision DSP block increase precision and performance for your application.

Training and Events

Workshop: BeMicro SDK Motor Control Kit Makes Design Easier
New BeMicro SDK Motor Control Kit lets you scale a motor control design easily in a single FPGA. Attend a hands-on workshop and get a free kit!

New Free Online Course: Variable-Precision DSP Blocks in FPGAs
Learn how the variable-precision DSP blocks in Stratix V, Arria® V, and Cyclone V FPGAs address today's signal processing challenges.

Updated Instructor-led Course: Quartus II Timing Analysis
Learn to constrain and analyze a design for timing using the latest features of the TimeQuest timing analyzer in Quartus II software v. 11.0

Updated Instructor-led Course: Advanced TimeQuest
Be more productive writing SDC files and performing timing analysis for advanced interfaces with the features in Quartus II v11.0 software.

Support and Literature

Run ModelSim-Altera Software Directly from Quartus II Software
Let Quartus II software set up your ModelSim®-Altera® simulation so you can focus on your design. This walkthrough shows you how.

Altera in the News

Radar Basics Part 2: Pulse Doppler Radar, EE Times
Read the second of a 5-part series on radar basics. Part 2 focuses on Pulse Doppler radar processing for target detection and discrimination.


Implementing Forward Error Correction in Optical Networking,
ATCA Newsletter
With growing bandwidth and OTN deployments evolving to 100G, there's an increase in FEC techniques to navigate the OTN landscape.


Most Popular News from Last Issue

5 New Qsys Technical Training Courses—Online and Instructor-Led
Select from 5 new training courses that will help you take advantage of the Qsys system integration tool in Quartus® II software. Choose from free one-hour online classes or 1-2 day courses. Learn how to build systems using Qsys, design with the Nios II processor and Qsys, and develop software for the Nios II Processor. Take a class now.

 
Buy Quartus II Software and Get a Free Nios II Processor

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