Aug News: Video Sneak Peak--See Stratix V FPGA Running at 28 Gbps

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August 2011   www.altera.com   Monthly Spotlight Video: Sneak Peek of Industry's First 28-Gbps FPGA See the performance of our 28-nm Stratix® V FPGA transceiver. Observe the transmit eye diagram at 28 Gbps running a PRBS-31 pattern and the receiver performance at 28 Gbps. Learn about the transceiver architecture that provides high performance, power efficiency, and reliability.   Technology and End Markets Video: 4 Reasons Why FPGAs Are Right for Motor Control See how to build a scalable motor control system in an FPGA, synchronize multiple motors, control a stepper motor, and use versatile design tools—all in one kit. Training and Events New Free Online Course: Stratix V FPGA Transceiver Design Flow Learn to create Stratix V FPGA transceiver designs using transceiver PHY intellectual property (IP) cores and build dynamic reconfiguration controller logic. Updated Free Online Course: Using the Quartus® II Chip Planner Learn to analyze a design using Chip Planner features such as floorplan views, critical path analysis, and routing congestion analysis. Support and Literature Simplify Package Selection with New Dynamic Packaging Datasheet Now it is easier to find the package and thermal resistance information for any Altera® device—with our new easy-to-use format and search tools. Altera in the News A Plan for Debug, EEWeb FPGAs are becoming increasingly complex, as are the associated designs. Read how to reduce the in-system debug cycle and improve design quality. Learn Radar Basics: Parts 3 to 5, EE Times Read the final three parts of this radar series: Beamforming and Radar Digital Processing, Space-Time Adaptive Processing, and Synthetic Aperture Radar. If you missed the first two articles, read Part 1 and Part 2. Most Popular News from Last Issue Design Checklist: Is Your FPGA Design Reusable? Read this article to learn how design reuse improves the quality of your FPGA design, shortens your design and verification cycle, and allows faster time to market. The design checklist helps you create a reusable FPGA design for your next project.   Click to enlarge To ensure that you receive future issues of the Inside Edge eNewsletter, please add announcements@altera.com to your address book. As a subscriber to the Inside Edge, you will receive a monthly email newsletter. To unsubscribe from this newsletter or manage all of your subscriptions please visit our Email Subscription Center. Subscribe to other Altera email updates: Product Announcements & Updates DSP eNewsletter Embedded eNewsletter Webcast & Video eNewsletter Technical Updates     Connect with Altera:            Copyright © 1995-2011 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.