Wednesday, 8 June 2011

June News: New Quartus II & Qsys Training, Webcasts, Tutorials

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Inside Edge Monthly Enewsletter
   June 2011   www.altera.com  

Monthly Spotlight
5 New Qsys Technical Training Courses—Online and Instructor-Led
Select from 5 new training courses that will help you take advantage of the Qsys system integration tool in Quartus® II software. Choose from free one-hour online classes or 1-2 day courses. Learn how to build systems using Qsys, design with the Nios II processor and Qsys, and develop software for the Nios II Processor. Take a class now.
    5 new Qsys training courses


Software, Intellectual Property, and Development Kits

New Webcasts: See How Qsys Will Save You Development Time
Whether you've used SOPC Builder for years, or you're new to system integration tools, see how Qsys can speed up your FPGA design development.


Tutorial: How to Build a Memory Test System with Qsys
Check out the step-by-step instructions on creating and verifying a design with the Qsys system integration tool in Quartus II software.

FPGAs, CPLDs, ASICs

White Paper: Optimize Power and Cost with Altera 28-nm Devices
Learn about the power and cost advantages of the 28-nm Altera® Stratix® V, Cyclone® V, Arria® V, and HardCopy® V devices.

MAX IIZ Multi-Touch Screen Reference Design (Altera Wiki)
Build your own multi-touch screen interface with MAX IIZ CPLDs and the help of Wiki user Jheape, who uploaded this reference design.

Technology and End Markets

White Paper: Optimize Motor Control with Integrated FPGA Flow
Read about an optimized DSP tool flow that reduces development time and provides a flexible, adaptable model for different drive systems.

White Paper: Leverage 28-nm FPGAs for Broadcast Equipment
Find out how to deliver the most highly integrated, lowest power, and lowest cost broadcast studio products with the latest 28-nm FPGAs.

Webcast: High-Performance DSP with Variable-Precision DSP Blocks
Learn how Arria V and Cyclone V FPGAs' variable-precision DSP block allows you to use the optimum precision at each stage of the DSP data path. Watch Webcast or read white paper.

White Paper: Using Floating-Point FPGAs for DSP in Radar
Learn about the advantages of using floating-point FPGAs in digital signal processing (DSP) radar applications.

Free Online Courses and Tutorials

What's New in Quartus II Software v11.0
Learn about new support added for Stratix V FPGAs, the new Qsys system integration tool, and several improvements to boost your productivity.

Quartus II Interactive Tutorial
Learn the basics of Quartus II software for a complete design flow. The "Guide" and "Test" features ensure success.

Support and Literature

Quartus II Software Handbook: Creating Your First Qsys System
Find out how to achieve up to 2X higher interconnect performance, improved design reuse, and support for hierarchical systems here.


From the Forum: Creating Multiple Frame-Buffer IP Design
Read this forum and join the discussion on how to create multiple DSP Builder designs without conflicting VHDL compilation.


Altera in the News

Radar Basics - Part 1, EE Times
Read the first of a 5-part series about the basics of radar and its many military and civilian applications.


Most Popular News from Last Issue


Video: See Stratix V FPGA Running at 14.1 Gbps—Now Shipping
Get a progress update on silicon checkout for production Stratix V FPGAs, the industry's first 28-nm high-end FPGAs. You'll also see an eye diagram illustrating transceiver performance. Samples of Stratix V FPGAs are now shipping. Watch the video today!

 
Download New Quartus® II Software v11.0 with Qsys

Video: 5 Reasons to Use MP32 in Your Custom Embedded Design

May Cartoon
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